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TTTC's Electronic Broadcasting Service |
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6th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
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Table-Top Demos and Corporate Support
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The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society. The workshop’s areas of interest include (but are not limited to) the following topics:
- Defects due to Wafer Thinning - Defects in Intra-Stack Interconnects - DfT Architectures for 3D-SICs - EDA Design-to-Test Flow for 3D-SICs - Failure Analysis for 3D-SICs - Fault-Tolerant Design for 3D-SICs - Interposer Testing - Known-Good Die / Stack Testing - Power and Heat Dissipation during Test - Pre-Bond, Mid-Bond and Post-Bond Test - Reliability of 3D-SICs - Stacking Yield of Dies and Interconnects - Standardization for 3D Testing - System/Board Test Issues for 3D-SICs - Test Cost Modeling for 3D-SICs - Test Flow Optimization for 3D-SICs - Tester Architecture incl. ATE and BIST - Thermal/Mechanical Stress in 3D-SICs - TSV Test, Redundancy, and Repair - Wafer Probing and Probe Marks of 3D-SICs |
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You are invited to participate and submit your contributions to the 3D-TEST Workshop. Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop’s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop. Publications – The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc. Table-Top Demos – The 3D-TEST Workshop offers the opportunity to present Table-Top Demos during the workshop. Table-Top Demo participants get a table and electricity outlet provided by the workshop. A Table-Top Demo presentation may include displaying slides or demoing tools. Typical content may be comprised of technical descriptions, case studies, best practices, and user testimonials of products or solutions. These presentations will be listed in the workshop program booklet along with the regular paper sessions, and should be targeted to the workshop’s technical audience. Table-Top Demos differ from other workshop presentations in that a company name, logo, and product name may be mentioned explicitly. Proposal selection is based on technical content and relevance to 3D-TEST audience and topics. Table-Top Demo tables will be assigned in a first-come-first-served order, but priority will be given to Corporate Supporters (see below). If you are interested in presenting a Table-Top Demo, please contact the workshop’s Program Chair Erik Jan Marinissen at <erik.jan.marinissen@imec.be.> Corporate Support – Companies are invited to provide financial support to the 3D-TEST Workshop. In return, the supporting corporations will be recognized by the workshop in various ways, including: display corporate logo on workshop’s website, program booklet, projection screen, Electronic Workshop Digest, etc. Corporate supporters get priority in the assignment of available Table-Top Demos. For additional details, please contact the workshop’s Finance Chair Bill Eklow at <beklow@cisco.com>. |
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Submission deadline: August 21, 2015 Notification of acceptance: September 4, 2015 Camera-ready material: September 20, 2015 |
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| Additional Information | |
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General Chair: Program Chair: Program Vice-Chair: |
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| Committee | |
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General Chair:
Program Chair / Vice Chair:
Finance Chair:
Panel Chair:
Publication Chair:
Publicity Chair:
Web Chair:
Arrangements Chair:
Program Committee Members:
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| For more information, visit us on the web at: http://3dtest.tttc-events.org |
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The 6th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
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IEEE
Computer Society- Test Technology Technical Council |
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TTTC CHAIR
PAST CHAIR
TTTC 1ST VICE CHAIR
SECRETARY
ITC GENERAL CHAIR TEST WEEK COORDINATOR TUTORIALS AND EDUCATION STANDARDS EUROPE MIDDLE EAST & AFRICA STANDING COMMITTEES ELECTRONIC MEDIA |
PRESIDENT OF BOARD SENIOR PAST CHAIR TTTC 2ND VICE CHAIR FINANCE IEEE DESIGN & TEST EIC TECHNICAL MEETINGS TECHNICAL ACTIVITIES ASIA & PACIFIC LATIN AMERICA NORTH AMERICA COMMUNICATIONS INDUSTRY ADVISORY BOARD |
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